1. Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to their processors, in particular, the control registers.
2. Background Information
All computer system processors include a number of control registers.sup.1 for controlling system operations. The number of control registers included and their specific usage vary from processor to processor. Some processors include only control registers for managing basic system operations, such as instruction fetching/execution (i.e. the program counter register), interrupt/exception handling and so forth. Other processors include additional control registers for controlling various hardware and/or operation mode selections, such as whether a processor is to operate in an "enhanced" mode or a backward compatible "emulation" mode, whether certain hardware checking is to be performed, whether certain interrupts are to be recognized, and so forth. Yet other processors further include control registers for assisting the operating system in managing system resources, such as memory management, process/context switching, procedure call and return, and so forth. FNT .sup.1 For the purpose of this application, the term "control registers" includes system registers, memory registers, and the like, used for controlling the operation of a computer system.
Typically, the control registers are included in an unorganized manner. In other words, there is no particular organizational relationship between one particular/group of control registers provided for one purpose with another particular/group of control registers provided for another purpose. As the number of control registers being provided continues to increase, it is desirable that the control registers be organized in some coherent manner.
Additionally, direct modifications of the control registers (as opposed to modifications made as a result of the normal course of instruction execution) are made through the use of special instructions (as opposed to using instructions from the standard instruction set). For security and system reliability reasons, these special instructions are usually available only to certain privileged processes. This conventional approach of employing special instructions has the disadvantage of burdening the instruction fetch and dispatch unit, due to the increased number of opcodes to be decoded. As processor speed continues to increase, an increasing number of instructions are required to keep the processors "fully" utilized. Thus, it is also desirable to be able to use instructions from the standard instruction set to directly modify the control registers, provided security and system reliability can be maintained.
As will be disclosed in more detail below, the present invention achieves these and other desirable results.